Celoxica RC203 Manual do Utilizador descarregar pdf (Página 5)

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RC200/203 Manual

www.celoxica.com

Assumptions & Omissions

This manual assumes that you:

• have used Handel-C or have the Handel-C Language Reference Manual

• are familiar with common programming terms (e.g. functions)

• are familiar with MS Windows

This manual does not include:

• instruction in VHDL or Verilog

• instruction in the use of place and route tools

• tutorial example programs. These are provided in the Handel-C User Manual

1 2 3 4 5 6 7 8 9 10 ... 89 90

Platform Developer’s Kit 1
Contents 3
Conventions 4
Assumptions & Omissions 5
1 RC200/203 board 6
2 RC200/203 overview 7
2.2 Professional kit 8
2.3 Expert kit 9
3 Installation and set-up 10
4 Hardware description 11
4.2 RC200/203 connectors 12
4.3 CPLD 12
4.3.1 Control and data pins 13
4.3.2 CPLD clock 14
4.4 FPGA 16
4.4.1 FPGA operation modes 17
4.5 Parallel port 21
4.7 ZBT SRAM banks 23
4.8 Clock generator (PLL) 25
4.9 Ethernet 26
4.10 Video input processor 27
4.11 Video output processors 28
4.12 Audio codec 30
4.15 7-segment displays 31
4.16 ATA / Expansion header 32
4.17 LEDs 34
4.18 Contact switches 35
4.19 Reset button 35
4.20 JTAG connector 35
4.22 Bluetooth module 37
4.23 Touch screen 37
5 RC200/203 PSL reference 40
5.2 Clock definitions 41
5.3 Detecting the board type 42
5.4 LED macros 42
5.5 Push button macros 43
5.6 Seven-segment macros 44
5.6.2 Writing digits 45
5.7 ZBT SRAM macros 46
5.7.3 Write address mask 47
5.7.4 Reading from RAM 47
5.8 PS/2 port macros 48
5.9 RS-232 port macros 50
Selecting the baud 51
Selecting the parity 52
Selecting the flow control 52
5.10 Touch screen macros 53
5.11 Video output macros 55
5.11.2 Enabling video output 57
5.11.3 Querying screen sizes 57
5.11.5 Writing a pixel 58
5.12 Video input macros 59
5.13 Audio I/O macros 63
5.14 Bluetooth macros 66
5.15 SmartMedia macros 68
Setting a logical address 73
Setting a physical address 74
Reading from the SmartMedia 74
Writing to the SmartMedia 75
5.16 Ethernet macros 76
Important considerations: 77
5.16.6 Reading a packet 79
Completing the read process 80
Starting the write process 81
5.17 Reconfiguring the FPGA 82
5.18 CPLD control 83
5.20 Expansion port pins 86
6 Index 87

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